1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop (DLL) circuit having a coarse lock time which adapts to a frequency band of an external clock signal by delaying the external clock signal by different cell delay times, and a semiconductor memory device having the DLL circuit.
2. Description of the Related Art
Synchronous semiconductor memory devices use a synchronization circuit for accurately synchronizing the phase of an internal clock signal with the phase of an external clock signal in order to prevent degradation of high-frequency operation performance. In general, a DLL circuit is used as the synchronization circuit for the synchronous semiconductor memory devices.
FIG. 1 is a block diagram of a conventional DLL circuit.
Referring to FIG. 1, a DLL circuit 100 includes a buffer 150, a delay circuit 110, a replica circuit 130, and a phase detector 140.
The buffer 150 buffers an external clock signal CLK. In response to a comparison signal XCOM, the delay circuit 110 generates an internal clock signal ICLK that is obtained by delaying an output signal of the buffer 150 by a predetermined time. The delay circuit 110 has a plurality of delay cells (not illustrated) that are connected in series.
The replica circuit 130 delays the internal clock signal ICLK by a data-path delay time, which is the time taken for the output data of a memory (not illustrated) to be outputted through a data path to an output pad, in response to the external clock signal CLK. The phase detector 140 generates the comparison signal XCOM corresponding to a phase difference between the external clock signal CLK and an output signal DQ_R of the replica circuit 130.
FIG. 2 is a timing diagram illustrating the conditions for transition from coarse lock to fine lock in the conventional DLL circuit illustrated in FIG. 1. In FIG. 2, DQ_R denotes an output signal of the replica circuit 130 and DQD_R denotes a signal that is obtained by delaying the output signal DQ_R by a predetermined time.
Referring to FIG. 2, the DLL circuit 100 compares the external clock signal CLK, the signal DQD_R, and the output signal DQ_R to perform a coarse lock operation. When a rising edge of the external clock signal CLK is in a lock window TW, the DLL circuit 100 performs a coarse lock operation. On the other hand, when a rising edge of the external clock signal CLK is not in a lock window TW, the DLL circuit 100 ends a coarse lock operation and starts a fine lock operation.
That is, when a rising edge of the external clock signal CLK is in a lock window TW (denoted by B), the DLL circuit 100 generates an ENDSTAGE signal to transition into a fine lock mode. On the other hand, when a rising edge of the external clock CLK is not in a lock window TW (denoted by A), the DLL circuit 100 further delays the internal clock signal ICLK by one delay cell (1 cell delay).
The lock window TW denotes a delay difference between the signal DQD_R and the output signal DQ_R. The ratio of a coarse lock time to a fine lock time changes depending on the size of the lock window TW. That is, when the size of the lock window TW increases, the coarse lock time decreases and the fine lock time increases. On the other hand, when the size of the lock window TW decreases, the coarse lock time increases and the fine lock time decreases.
In general, a DLL circuit for a memory system is designed to be optimal for a high-frequency operation. That is, a DLL circuit optimized for a high-frequency operation is designed to have a narrow lock window. However, because a DLL circuit for a memory device operates in a wide frequency band, the use of the DLL circuit optimized for the high-frequency operation increases a coarse lock time for a low frequency, which may lead to a shortage of the lock time.
In addition, because the DLL circuit optimized for the high-frequency operation is designed to have a small cell delay, a long time is taken for the coarse lock for the low frequency.